1. Field of the Invention
The present invention relates to a wafer bevel etching apparatus stand and the related method of flattening a wafer, and especially a method of flattening a wafer by utilizing a wafer bevel etching apparatus.
2. Description of the Prior Art
In processes of manufacturing semiconductor devices, material layers, such as a plurality of polysilicon layers, a plurality of metal interconnecting layers and a plurality of dielectric layers with low dielectric constants (low-k), are usually used to form these semiconductor devices or integrated circuits. However, the material layers deposited on the wafer usually have non-uniform thicknesses, or have surfaces of non-uniform horizontal height, so the surface of integrated circuit has a severe topography. As a result, it affects the subsequent processes, such as the chemical mechanical polishing (CMP) processes, the pattern transferring processes, or deposition processes of forming other material layers. As the sizes of semiconductor devices get into a level of deep microns, the CMP process is utilized to polish target thin films, such as materials on a semiconductor wafer, for planarity and uniformity, so all semiconductor chips can have a flat surface, and the yield of the subsequent processes can be ensured.
In regard to the traditional processes, the problem of non-uniform thicknesses is particularly obvious around the wafer bevel, and parts of the wafer are relatively thick on the wafer bevel. Although a CMP process can be performed for flattening after the deposition process, the thick film on the wafer bevel obstructs the CMP slurry, and affects the polishing stress distribution. In addition, the traditional CMP apparatus also has limitations, so this CMP process actually cannot effectively control the edge topography of the wafer, and the wafer still has a severe profile.
Please refer to FIG. 1, which is a schematic diagram showing the relationship between the thicknesses and the positions of a wafer formed by a traditional method, where the x-coordinate refers to the distance from the center of the wafer, and the y-coordinate refers to the thicknesses of the material layer on the wafer. The measured wafer undergoes a deposition process of an inter-layer dielectric (ILD) layer, a CMP process, and a wafer bevel rinse (WBR) process. As shown in FIG. 1, the film thickness of the wafer bevel and the film thickness of the center can have a difference of 800 angstroms (A). The thicker wafer bevel not only affects the performance of the CMP process, but also includes more defects therein. These defects also affect the performance of following processes, and the subsequently formed devices or structures therefore have defects therein. Take the process of forming contact plugs as an instance. Although all the contact holes are etched in the same etching process, the contact holes near the wafer bevel cannot expose the underlying devices due to the thicker ILD layer on the wafer bevel. Thus, the formed contact plugs are not electrically connected to the underlying devices, and open defects occur. On the other hand, the bevel defects on the wafer bevel can also affect the following etching processes or other deposition processes. For example, it is observed that more unwanted nodules are formed in the following etching process while the material layer of the wafer bevel is thicker.
In light of this, many of the product wafers do not pass the wafer acceptance test (WAT), and the yield is therefore decreased. As a result, it is still a challenge to form a material layer having uniform thickness, and to control the edge topography.